Memory-Map Navigator v4.2.1 Build 414 serial key or number
Memory-Map Navigator v4.2.1 Build 414 serial key or number
Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express Design Example User Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite |
| IP Version |
The following table summarizes the configurations to be supported by the P-Tile Avalon®-MM design examples:
| Gen3/Gen4 x16 | Gen3/Gen4 x8 | Gen3/Gen4 x4 | |
|---|---|---|---|
| Endpoint (EP) | Yes 1 | Yes | N/A |
| Root Port (RP) | 2 | N/A | Yes |
This DMA design example includes a DMA Controller and an on-chip memory to exercise the Data Movers.
The design example also connects the Bursting Master (in non-bursting mode) to the on-chip memory to allow high-throughput transfers should the host or some other component of the PCIe system be capable of initiating such transfers (e.g. a Root Complex with a DMA engine).
The on-chip memory that the Data Movers and the Bursting Master connect to is a dual-port memory to allow full-duplex data movement.
The Bursting Master connects to a BAR Interpreter module, which combines the address and BAR number and allows the Bursting Master to control the DMA Controller. The BAR Interpreter also connects the Bursting Master to the dual-port memory.
| Resource | Address Range | BAR |
|---|---|---|
| DMA | 0x0 - 0x0FFFF | 0 |
| MEM0.s1 | 0x - 0x27FFF | 2 |
| MEM0.s2 | 0x - 0x2FFFF | 4 |
The design example is generated dynamically based on the selected variation of the P-Tile Avalon®-MM IP for PCIe. However, some of the user’s parameter selections may need to be overwritten to ensure proper functionality. A warning appears when such a need arises.
In the release of Intel® Quartus® Prime, the only variation supported is the DMA variation. This variation instantiates the Bursting Master (in non-bursting mode), Read Data Mover and Write Data Mover. Software sends instructions via the Bursting Master to the Read or Write Data Movers to initiate DMA Reads or Writes to the system memory. The BAR Interpreter, on-chip memory and DMA Controller are also included.
- DUT: The P-Tile Avalon-MM IP for PCIe Endpoint.
- MEM0: An on-chip dual-port memory that connects to the Read Data Mover and Write Data Mover interfaces of the DUT.
- DMA_CONTROLLER: A DMA Controller that interfaces with the normal and priority descriptor queues of the DUT's Read Data Mover and Write Data Mover.
- BAR_INTERPRETER: A BAR Interpreter that combines the address and BAR number to form a wider address that Platform Designer can use to route memory transactions to the various slaves. The BAR Interpreter connects the Bursting Master of the DUT to the dual-port memory.
- Reset Release IP: This IP holds the control circuit in reset until the device has fully entered user mode. The FPGA asserts the output to signal that the device is in user mode. The Reset Release IP generates an inverted version of the internal signal to create the output that you can use for your design.The signal is high until the entire device enters user mode. After asserts (low), all logic is in user mode and operates normally. You can use the signal in one of the following ways:
- To gate an external or internal reset.
- To gate the reset input to the transceiver and I/O PLLs.
- To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers.
- To synchronously drive register reset input ports in your design.
| Slave | BAR_manicapital.com_master | dut.p0_wrdm_master | dut.p0_rddm_master | dut.p0_bam_master |
|---|---|---|---|---|
| BAR_manicapital.com_slave | 0x___ - 0x___ffff | |||
| DMA_manicapital.com_slave | 0x_ - 0x_0fff | 0x___ - 0x___0fff | ||
| MEM0.s1 | 0x_ - 0x_7fff | 0x___ - 0x___7fff | ||
| MEM0.s2 | 0x_ - 0x_ffff | 0x___ - 0x___7fff |
The DMA Controller in this example design consists of six addressable queues: two write-only queues and one read-only queue each for the Read Data Mover and the Write Data Mover. In addition, the DMA Controller has two MSI control registers for each Data Mover module.
The write-only queues directly feed into the Data Movers’ normal and priority descriptor queues. The read-only queues read directly from the Data Movers’ status queues.
The MSI control registers control whether MSI generation is enabled and defines the address and data to be used for the MSI.
The example design uses generated from the clock.
The registers in the DMA Controller are bit wide to match the data path width of the Bursting Master's and Read Data Mover's Avalon®-MM Master. This allows the Read Data Mover to write a descriptor in a single cycle if desired.
| Offset | Name | Access | Description |
|---|---|---|---|
| 0x | WDN | R/W | write: descriptor for the Write Data Mover normal descriptor queue read: readiness and fill level of the Write Data Mover normal descriptor queue |
| 0x | WDP | R/W | write: descriptor for the Write Data Mover priority descriptor queue read: readiness and fill level of the Write Data Mover priority descriptor queue |
| 0x | WS | RO | Write Data Mover status queue |
| 0x | WI | R/W | Write Data Mover interrupt control register |
| 0x | RDN | R/W | write: descriptor for the Read Data Mover normal descriptor queue read: readiness and fill level of the Read Data Mover normal descriptor queue |
| 0xA00 | RDP | R/W | write: descriptor for the Read Data Mover priority descriptor queue read: readiness and fill level of the Read Data Mover priority descriptor queue |
| 0xC00 | RS | RO | Read Data Mover status queue |
| 0xE00 | RI | R/W | Read Data Mover interrupt control register |
For the data written to the descriptor queue registers, use the same format and content as the data on the corresponding Avalon®-ST interfaces of the Data Movers. The least significant of the application specific bits indicates whether an interrupt should be issued when processing of that descriptor completes. The data is written to the least significant bits of the registers because the descriptors are bit wide (refer to Table 6 for the descriptor format).
The DMA Controller double buffers the write-only queues so that the descriptors can be built one DWORD at a time if required, for example by a bit host controller. The content of the register is transferred to the Data Movers' Avalon®-ST input when the most significant DWORD is written.
Attempting to write to a descriptor queue when the corresponding Data Mover's signal is not asserted causes the DMA Controller to assert its signal until is asserted. You must make sure the Read Data Mover does not attempt to write to the same queue that it is processing while the queue is full, as that would lead to a deadlock. For more details on deadlocks, refer to the section Deadlock Risk and Avoidance.
You can find the status of the signal of a descriptor queue interface by checking the bit (bit [31]) of the queue registers. In addition, bits [] of the queue registers indicate the approximate fill level of the queues. The other bits of the queue registers are set to 0.
Only the least significant DWORD of the WS and RS registers contains significant information. The other bits are set to 0.
The format and content of the status queues are identical to the corresponding Avalon®-ST interfaces of the Data Movers with the addition of bit 31 indicating that the queue is empty. Reading from one of the status queues when it is empty returns 'h_
The format of the WI and RI interrupt control registers is as follows: .
The bit controls whether or not an MSI is sent. The bit specifies whether to use the priority queue to send the MSI. The MSI memory write TLP also uses the contents of the and fields.
Under certain circumstances, it is possible for the DMA engine in the design example hardware to get into a deadlock. This section describes the conditions that may lead to a deadlock, and how to avoid them.
When you program the DMA Controller to use the Read Data Mover to fetch too many descriptors for the Read Data Mover descriptor queue, the following loop of backpressure that leads to a deadlock can occur.
Once the Read Data Mover has transferred enough descriptors through the DMA Controller to its own descriptor queue to fill up the queue, it deasserts its ready output. The DMA Controller in turn asserts its waitrequest output, thus preventing the Read Data Mover from writing any remaining descriptor to its own queue. After this situation occurs, the Read Data Mover continues to issue MRd read requests, but because the completions can no longer be written to the DMA Controller, the tags associated with these MRd TLPs are not released. The Read Data Mover eventually runs out of tags and stops, having gotten into a deadlock situation.
To avoid this deadlock situation, you can limit the number of descriptors that are fetched at a time. Doing so ensures that the Read Data Mover's descriptor queue never fills up when it is trying to write to its own descriptor queue.
Two application specific bits (bits []) of the status words from the Write Data Mover and Read Data Mover Status Avalon®-ST Source interfaces control when interrupts are generated.
| Bit [13] | Bit [12] | Action |
|---|---|---|
| 1 | 1 | Interrupt always |
| 1 | 0 | Interrupt if error |
| 0 | 1 | No interrupt |
| 0 | 0 | No interrupt and drop status word (i.e, do not even write it to the WS or RS status queues) |
The DMA Controller makes the decision whether to drop the status word and whether to generate an interrupt as soon as it receives the status word from the Data Mover. When generation of an interrupt is requested, and the corresponding RI or WI register does enable interrupts, the DMA Controller generates the interrupt. It does so by queuing an immediate write to the Write Data Mover's descriptor queue specified in the corresponding interrupt control register using the MSI address and message data provided in that manicapital.com need to make sure that space is always available in the targeted Write Data Mover descriptor queue at any time when an interrupt may get generated. You can do so most easily by using the priority queue only for MSIs.
Setting the interrupt control bits in the immediate write descriptors that the DMA Controller creates to generate MSI interrupts to "No interrupt and drop status word" can avoid an infinite loop of interrupts.
To initiate a single DMA transfer, you only need to write a well-formed descriptor to one of the DMA Controller's descriptor queues (WDN, WDP, RDN or RDP).
To initiate a series of DMA transfers, you can prepare a table of descriptors padded to bits each in a memory location accessible to the Read Data Mover. You can then write a single descriptor to the DMA Controller's priority descriptor queue (RDP) register to initiate the DMA transfers. These transfers move the descriptors from the source location in PCIe memory to the desired descriptor queue register.
To transmit an MSI interrupt upon completion of the processing of a descriptor, you must program the DMA Controller's WI or RI register with the desired MSI address and message before writing the descriptor.
The Bursting Slave module transforms read and write transactions on its Avalon®-MM interface into PCIe memory read (MRd) and memory write (MWr) request packets. The Bursting Slave uses the Avalon®-MM address provided on its bit wide address bus directly as the PCIe address in the TLPs that it creates.
The Bursting Slave, with its bit address bus, uses up the whole Avalon®-MM address space and prevents other slaves from being connected to the same bus. In many cases, the user application only needs to access a few relatively small regions of the PCIe address space, and would prefer to dedicate a smaller address space to the Bursting Slave to be able to connect to other slaves.
The Bursting Master module transforms PCIe memory read and write request packets received from the PCIe system into Avalon®-MM read and write transactions. The offset from the matching BAR is provided as the Avalon®-MM address, and the number of the matching BAR is provided in a conduit synchronously with the address.
Although these signals are in a conduit separate from the Avalon®-MM master interface, they are synchronous to it and can be treated as extensions of the address bus.
The BAR Interpreter simply concatenates the BAR number to the address bus to form a wider address bus that Platform Designer can now treat as a normal address bus and route to the various slaves connected to the BAR Interpreter.
- In system memory, prepare a contiguous set of descriptors. The last of these descriptors is an immediate write descriptor, with the destination address set to some special system memory status location. The descriptor table must start on a byte aligned address. Even though each descriptor is only about bit long, bits are reserved for each descriptor. The descriptors are LSB-aligned in that bit field.
- In system memory, prepare one more descriptor which reads from the beginning of the descriptors from Step 1 and writes them to a special FIFO Avalon®-MM address in FPGA.
- Write the descriptor in Step 2 to the same special FIFO Avalon®-MM address by:
- Writing one dword at a time, ending with the most significant dword.
- Writing three dwords of padding and the entire descriptor for a total of eight dwords (the descriptor takes up only five dwords, but CPUs do not typically support single-TLP, five-dword writes).
- Poll the special status location in system memory to see if the final immediate write has occurred, indicating the DMA completion.
The Read and Write Data Movers uses descriptors to transfer data. The descriptor format is fixed and specified below:
| Signals Description (for or ) | Read Data Mover | Write Data Mover |
|---|---|---|
| []: reserved | N/A | N/A |
| []: descriptor ID | ID of the descriptor | ID of the descriptor |
| []: application-specific | Application-specific bits. Example of an Intel application is provided below. | Application-specific bits. Example of an Intel application is provided below. |
| []: single destination | When the single destination bit is set, the same destination address is used for all the transfers. If the bit is not set, the address increments for each transfer. | N/A |
| []: single source | N/A | When the single source bit is set, the same source address is used for all the transfers. If the bit is not set, the address increments for each transfer. Note that in single source mode, the PCIe address and Avalon-MM address must be byte aligned. |
| []: immediate | N/A | When set, the immediate bit indicates immediate writes. Immediate writes of one or two dwords are supported. For immediate transfers, bits [] or [] contain the payload for one- or two-dword transfers respectively. The two-dword immediate writes cannot cross a 4k boundary. This can be used for MSI/MSI-X for example. |
| []: transfer size | Number of dwords to transfer. | Number of dwords to transfer (up to dwords, or 32 kB, per descriptor). |
| []: destination address | Avalon-MM address | PCIe Address |
| []: source address | PCIe Address | Avalon-MM address |
Application-Specific Bits
Three application-specific bits (bits [] ) from the Write Data Mover and Read Data Mover Status Avalon-ST Source interfaces control when interrupts are generated.
| Bit [] | Bit [] | Bit [] | Action |
|---|---|---|---|
| 0 | 1 | 1 | Interrupt always |
| 0 | 1 | 0 | Interrupt if error |
| 0 | 0 | 1 | No interrupt |
| 0 | 0 | 0 | No interrupt and drop status word |
The External DMA Controller makes the decision whether to drop the status word and whether to generate an interrupt as soon as it receives the status word from the Data Mover. When the generation of an interrupt is requested, and the corresponding RI or WI register does enable interrupts, the DMA Controller generates the interrupt. It does so by queuing an immediate write to the Write Data Mover's descriptor queue (specified in the corresponding interrupt control register) using the MSI address and message data provided in that register.
A Read DMA transfers data from the PCIe address space (system memory) to the Avalon-MM address space. It sends Memory Read TLPs upstream, and writes the completion data to local memory in the Avalon-MM address space using the Read Data Mover's Avalon®-MM write master interface.
- Prepare a table of descriptors (padded to bit each) to perform the Read operation and put the table into the system memory.
- Using the BAM, send one descriptor from software containing the address of the descriptor table to the DMA Controller, which forwards it to the Read Data Mover.
- The Read Data Mover fetches the descriptor table and puts it in a FIFO inside the DMA Controller.
- The DMA Controller outputs these descriptors to the Read Data Mover based on the readiness of the Read Data Mover (indicated by an asserted or signal).
- The Read Data Mover processes the descriptors by fetching data from the system memory, and writing it to the appropriate Avalon®-MM memory.
- The last descriptor processed by the Read Data Mover points to an immediate write descriptor (i.e, a descriptor where the data to be written is inside the descriptor itself) in the system memory. This descriptor's destination address is the Avalon® memory address of the DMA Controller's Write Data Mover port. The Read Data Mover fetches this descriptor from system memory and transfers it to the DMA Controller's Write Data Mover Avalon® address.
- The Write Data Mover uses the descriptor from Step 6 to perform an immediate write to the system memory indicating the completion of the Read Data Mover’s data processing.
A Write DMA transfers data from the Avalon-MM address space to the PCIe address space (system memory). It uses the Write Data Mover's Avalon®-MM read master to read data from the Avalon®-MM address space and sends it upstream using Memory Write TLPs.
- Prepare a table of descriptors (padded to bit each) to perform the Write operation and put the table into the system memory.
- Using the BAM, send one descriptor from software containing the address of the descriptor table to the DMA Controller, which forwards it to the Read Data Mover.
- The Read Data Mover fetches the descriptor table and puts it in a FIFO inside the DMA Controller.
- The DMA Controller outputs these descriptors to the Write Data Mover based on the readiness of the Write Data Mover (indicated by an asserted or signal).
- The Write Data Mover processes the descriptors by fetching data from the Avalon®-MM memory, and writing it to the appropriate system memory.
- The Write Data Mover uses the last descriptor in the descriptor table to indicate the completion of the Write Data Mover’s data processing. This descriptor is an Immediate Write (the data is inside the descriptor itself) to the system memory indicating the Write Data Mover’s operations are done.
- Gen3 x4 with x4 bifurcation Root Port
- Gen4 x4 with x4 bifurcation Root Port
The RP design example performs enumeration and configuration of the PCI Express hardware by using the RP Master system script running on System Console. The RP Master system script configures the RP itself through the P-Tile Hard IP Reconfiguration interface and discovers the PCI Express hardware by performing CfgRd and CfgWr transactions and BAR initialization via the Control Register Access (CRA) Avalon®-MM Slave interface.
The RP design example automatically creates the files necessary to compile in the Intel® Quartus® Prime software. It also generates the RP Master system script (.tcl) which can run on System Console.
- DUT: This is the generated Intel P-Tile Avalon®-MM PCIe IP Root Port variant configured with the parameters you specified. The DUT supports x4 bifurcation mode in the RP configuration. It has the following interfaces enabled (note that only Port 0 (P0) is utilized):
- P0 Control Register Access (CRA) Avalon®-MM Slave port.
- P0 Avalon®-MM Slave interface with individual byte access (TXS).
- P0 Hard IP (HIP) dynamic reconfiguration interface of PCIe registers.
- RP_MASTER: This is the JTAG to Avalon® Master Bridge Intel FPGA IP. It is a driver that converts the memory read/write commands from the RP Master system script running in System Console to Avalon®-MM transactions that are sent to the DUT.
- Control Register Access (CRA) Avalon®-MM Slave: This module is used to issue accesses to the Endpoint's configuraiton space registers. It supports a single transaction at a time. It converts single-cycle, bit Avalon®-MM read and write transactions into PCIe configuration read and write TLPs (CfgRd0, CfgRd1, CfgWr0 and CfgWr1) to be sent over the PCIe link.
- Non-bursting Avalon®-MM (TXS) Slave: This module has a bit wide data bus. It converts single-cycle, bit Avalon®-MM read and write transactions into PCIe memory read and write TLPs (MemRd, MemWr) to be sent over the PCIe link.
- Hard IP Reconfiguration Avalon®-MM Slave: This interface has a bit address bus and an 8-bit data bus. The application logic (RP Master) uses this interface to access its PCIe configuration space to perform link control functions (such as Hot Reset, link disable, or link retrain).
| Components | Base Address | Range |
|---|---|---|
| Hard IP Reconfiguration interface | 0x_ | 0x20_ |
| CRA interface | 0x_ | 0x |
| TXS interface | 0x_ | 0x_ |
For more details on the CRA interface register map, refer to the Programming Model for the Avalon®-MM Root Port chapter of the Intel® Stratix® 10 H-Tile and L-Tile Avalon® memory mapped Hard IP for PCI Express User Guide.
- The Endpoint DMA design example cannot handle bit tags.
- To enable the Gen4 x16 Endpoint DMA design example to meet timing requirements at MHz, you need to manually enable all pipelinable locations in the Platform Designer Interconnect fabric (). Here are the steps to enable the pipeline stages:
- Open the generated design example in Platform Designer.
- Click on System, then Show System with Platform Designer Interconnect.
- Click on Show Pipelinable Locations.
- Go through each and enable all pipelinable registers for both Command and Response.
- Generate the HDL for the design example.
- Simulation is supported for the Endpoint design example in the release of Intel® Quartus® Prime, but it is available for the VCS simulator only.
- Simulation is not supported for the Root Port design examples in the release of Intel® Quartus® Prime, but will be supported in a future release.
Using Intel® Quartus® Prime Pro Edition, you can generate a simple Endpoint (EP) DMA design example or a Root Port (RP) design example for the P-Tile Avalon®-MM IP for PCI Express IP core.
The generated design example reflects the parameters that you specify. It automatically creates the files necessary to simulate and compile the design example in the Intel® Quartus® Prime Pro Edition software. You can download the compiled design example to the Intel® Stratix® 10 DX Development Board or Intel® Agilex™ Development Board to do hardware testing. To download to custom hardware, update the Intel® Quartus® Prime Settings File (.qsf) with the correct pin assignments.
The RP design example transfers RP commands from the RP Master system script running in System Console to the Endpoint PCIe device. It supports link status checking between the RP and EP, RP configuration, EP enumeration and BAR initialization.
The available design example is for an Endpoint with a single function. This DMA design example includes a DMA Controller and an on-chip memory to exercise the Data Movers in the P-Tile Avalon-MM IP for PCI Express.
- In the Intel® Quartus® Prime Pro Edition software, create a new project (File → New Project Wizard).
- Specify the Directory Name, and Top-Level Entity.
- For Project Type, accept the default value, Empty project. Click Next.
- For Add Files click Next.
- For Family, Device & Board Settings under Family, select Intel® Agilex™ or Intel® Stratix®
- If you select Intel® Stratix® 10 in the last step, select Stratix 10 DX in the Device pull-down menu.
- Select the Target Device for your design.
- Click Finish.
- In the IP Catalog locate and add the Intel P-Tile Avalon®-MMIP for PCI Express* .
- In the New IP Variant dialog box, specify a name for your IP. Click Create.
- On the Top-Level Settings and PCIe* Settings tabs, specify the parameters for your IP variation. For example, select Root Port for the RP variant.
- On the Example Designs tab, make the following selections:
- For Example Design Files, turn on the Synthesis option. If you do not need these synthesis files, leaving the corresponding option turned off significantly reduces the example design generation time.Note: Simulation is not supported for the RP design example in the release of Intel® Quartus® Prime. It will be supported in a future release. Therefore, if you are working with the RP design example, turn on the Synthesis option only. Do not turn on the Simulation option.
- For Generated HDL Format, only Verilog is available in the current release.
- For Target Development Kit, select the appropriate option. For the current release, the supported development kits are:
- Intel® Stratix® 10 DX P-Tile ES1 FPGA Development Kit
- Intel® Agilex™ F-Series P-Tile ES0 FPGA Development Kit
- For Example Design Files, turn on the Synthesis option. If you do not need these synthesis files, leaving the corresponding option turned off significantly reduces the example design generation time.
- Select Generate Example Design to create a design example that you can compile and download to hardware. If you select one of the P-Tile development boards, the device on that board overwrites the device previously selected in the Intel® Quartus® Prime project if the devices are different. When the prompt asks you to specify the directory for your example design, you can accept the default directory, <project_dir>/intel_pcie_ptile_avmm_0_example_design, or choose another directory.Figure 9. Example Designs Tab
- Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the example design.
- Open the example design project.
- Compile the example design project to generate the .sof file for the complete example design. This file is what you download to a board to perform hardware verification.
- Close your example design project.
- Change to the testbench simulation directory, intel_pcie_ptile_avmm_0_example_design\pcie_ed_tb.
- Run the simulation script for VCS. Refer to the table below.
- Analyze the results.
| Simulator | Working Directory | Instructions |
|---|---|---|
| VCS* |
PMC
4. Discussion
In this study, we demonstrate that amnesic patients with primary damage to the hippocampus bilaterally were unable to solve a novel associative learning task whose solution necessitated the acquisition of configural information. Our results show that patients were similarly impaired at configural learning within the spatial and non-spatial domains. Further, our findings demonstrate that residual configural learning can occur in the presence of hippocampal dysfunction. Moreover, we observed that such residual learning was associated with explicit knowledge of the relevant task contingencies in a post-experimental debriefing session. However, patients performed poorly when asked to estimate outcome probabilities in more general situations, suggesting that their knowledge of the task structure was relatively inflexible and concrete in nature. Interestingly, the explicit knowledge demonstrated by patients in the debriefing session appeared to correspond with the best-fit strategy identified by our strategy analysis. These findings therefore suggest that residual learning in patients relies upon regions within the MTL, rather than a striatal-based system often engaged when learning is supervised (i.e. feedback is given) and occurs over numerous trials. In summary, our results support the view that the hippocampus plays an important role in both spatial and non-spatial configural learning, and provide insights into the role of the MTL more generally in incremental reinforcement-driven learning.
Our findings demonstrate that the human hippocampus participates in both spatial and non-spatial configural learning. This contrasts with recent findings that rats with hippocampal lesions were selectively impaired at a spatial, but not a non-spatial, configural task (Sanderson et al.,
Released 9/15/
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Released 9/1/
Features:
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- With enabled, the command is available.
- By using , your tests can intercept, modify, and wait on any type of HTTP request originating from your app, including s, requests, beacons, and subresources (like iframes and scripts).
- Outgoing HTTP requests can be modified before reaching the destination server, and the HTTP response can be intercepted as well before it reaches the browser.
- See the docs for more information on how to enable this experiment.
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Released 8/19/
Summary:
Cypress now includes support for test retries! Similar to how Cypress will retry assertions when they fail, test retries will allow you to automatically retry a failed test prior to marking it as failed. Read our new guide on Test Retries for more details.
Breaking Changes:
Please read our Migration Guide which explains the changes in more detail and how to change your code to migrate to Cypress
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- The configuration flag has been removed, since this behavior is now the default. Addresses #
- The return type of the methods , , , and have changed from to . Addresses #
- Cypress no longer supports file paths with a question mark in them. We now use the webpack preprocessor by default and it does not support files with question marks. Addressed in #
- For TypeScript compilation of spec, support, and plugins files, the option is no longer coerced to . If you need to utilize , set it in your . Addresses #
- Cypress now requires TypeScript +. Addressed in #
- Installing Cypress on your system now requires manicapital.com 10+. Addresses #
- In spec files, the values for the globals and no longer include leading slashes. Addressed in #
Features:
- There&#x;s a new configuration option to configure the number of times to retry a failing test. Addresses #
- , , and now accept options , , , and to hold down key combinations while clicking. Addresses #
- You can now chain off of and to disabled snapshots during those commands. For example: . Addresses #
Bugfixes:
- The error will no longer incorrectly throw when rerunning tests in the Test Runner. Fixes # and #
- Cypress will no longer throw a error during on Firefox versions >= Fixes #
- The error will no longer throw when calling on an element in the shadow dom. Fixes #
- Cypress environment variables that accept arrays as their value will now properly evaluate as arrays. Fixes #
- Elements having will no longer be considered hidden if it has child elements within it that are visible. Fixes #
- When is enabled, and commands now work correctly in shadow dom as well as passing a selector to when the subject is in the shadow dom. Fixed in #
- Screenshots will now be correctly taken when a test fails in an or hook after the hook has already passed. Fixes #
- Cypress will no longer report screenshots overwritten in a option as a unique screenshot. Fixes #
- Taking screenshots will no longer fail when the screenshot names are too long for the filesystem to accept. Fixes #
- The last used browser will now be correctly remembered during if a non-default-channel browser was selected. Fixes #
- For TypeScript projects, will now be loaded and used to configure TypeScript compilation of spec and support files. Fixes # and #
- now correctly show the number of passed and failed tests when a test passes but the fails. Fixes #
- The Developer Tools menu will now always display in Electron when switching focus from Specs to the Test Runner. Fixes #
Documentation Changes:
Misc:
- Cypress now uses the webpack preprocessor by default to preprocess spec files.
- The Runs tab within the Test Runner has a new improved design when the project has not been set up or login is required. Addressed in #
- The type for the object returned from is now correct. Addresses #
- The type definition for Cypress&#x;s can now be extended. Addresses #
- The type definition for has been added. Addresses #
Dependency Updates
- Upgraded Chrome browser version used during cypress run and when selecting Electron browser in cypress open from to . Addressed in #
- Upgraded bundled manicapital.com version from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in # and #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
Released 8/5/
Bugfixes:
- The error will no longer incorrectly throw when rerunning tests in the Test Runner. Fixes #
- Skipping the last test before a nested suite with a hook will now correctly run the tests in the suite following the skipped test. Fixes #
Dependency Updates:
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
Released 8/3/
Features:
- Now you can control whether screenshots are automatically taken on test failure during by setting in your configuration. Addresses #
- The now has access to a readonly property within the object that returns the current Cypress version being run. This will allow plugins to better target specific Cypress versions. Addresses #
- During , you can now run a subset of all specs by entering a text search filter and clicking &#x;Run n tests&#x;. Addresses #
Bugfixes:
- elements that have a parent with will now correctly evaluate as visible. Fixes #
- Applications using custom elements will no longer trigger infinite XHR request loops. Fixes #
- When snapshotting the DOM, Cypress no longer causes to be triggered on custom elements. Fixes #
- Spec files containing characters now properly run in Cypress. Fixes #
- When using the shortcut in , an error is now thrown when the fixture file cannot be found. Fixes #
- Cypress no longer thrown error when passing a file containing content to . Fixes #
- Values containing exponential operators passed to via the command line are now properly read. Fixes #
- The Open in IDE button no longer disappears from hooks when the tests are manually rerun. Fixes #
- When is enabled, AST rewriting will no longer return an output before the body is done being written. This would happen when the response body was too large and the response would be sent while the body was still being modified. Fixes #
- When using , Cypress now properly types into an input within an iframe that auto focuses the input. Fixes #
Misc:
- Dependencies for our npm package are no longer pinned to a specific version. This allows the use of to fix security vulnerabilities without needing a patch release from Cypress. Addresses #
- We now collect environment variables for AWS CodeBuild when recording to the Dashboard. Addressed #
- Types inside Module API are now accessible via the namespace. Addresses #
- We added more type definitions for the command. Addresses #
- Cookie command&#x;s property type is now a Number instead of a String. Addresses #
- There are some minor visual improvements to the Test Runner&#x;s Command Log when hovering, focusing and clicking on hook titles and pending tests. Addressed in #
Dependency Updates:
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
Released 7/21/
Features:
- You can now pass an option to to skip checking whether the element is scrollable. Addresses #
- now accepts Dates as well as a Number for now. Fixes #
- The Module API has a new function to assist in parsing user-supplied command line arguments using the same logic as uses. Addesses #
Bugfixes:
- Running multiple specs within Firefox during on Windows will no longer fail trying to make a connection to the browser. Fixes #
- Cypress will no longer throw a error during on Firefox versions >= Fixes #
- Fixed an issue where Cypress tests in Chromium-family browsers could randomly fail with the error WebSocket is already in CLOSING or CLOSED state. Fixes #
- Taking a screenshot of an element that changes height upon scroll will no longer throw an error. Fixes #
- Setting or from within the test configuration now properly changes the viewport size for the duration of the suite or test.
- Setting deep objects and arrays on within the now sets the values correctly. Fixes #
- The progress bar for now reflects the correct and of the command. Fixes #
- The command&#x;s progress bar will not longer restart when its parent test is collapsed in the Command Log. Fixes #
- Key value pairs sent to as will now be properly read in. Fixes #
- Stubbed responses responding with an empty string to now correctly display as &#x;xhr stub&#x; in the Test Runner&#x;s Command Log. Fixes #
- Quickly reclicking the Run All Tests button in the Test Runners&#x; Command Log will no longer throw errors about undefined properties and the tests will no longer hang. Fixes #
Misc:
- The error messages thrown from and now mention that extensions are supported. Addresses #
- The style when focusing on tests in the Command Log has been updated. Addresses #
Dependency Updates:
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #, #, and #
Released 7/7/
Features:
- You can open a , , , and hook definition in your IDE from the Test Runner&#x;s Command Log by clicking the Open in IDE button. Addresses #
- , , , and hook definitions now display separately in the Test Runner&#x;s Command Log when defined in separate hook definitions. Addresses #
- You can now open a spec file directly from the Tests tab in the Test Runner by clicking the Open in IDE button. Addresses #
Bugfixes:
- HTTP requests taking longer than the default will no longer be prematurely canceled by the Cypress proxy layer. Fixes #
- Using Cypress commands to traverse the DOM on an application with a global variable will no longer throw Illegal Invocation errors. Fixes #
- When is enabled, using on an input in the Shadow DOM will not result in an error. Fixes #
- When is enabled, checking for visibility on a shadow dom host element will no longer hang if the host element was the foremost element and had an ancestor with fixed position. Fixes #
- Debug logs from the module will no longer appear if any environment variable was set. Fixed #
Misc:
- We made some minor UI updates to the Test Runner. Addresses # and #
Dependency Updates:
- Upgraded from to . Addressed in #
Released 6/23/
Features:
- An animated progress bar now displays on every command in the Command Log indicating how long the command has left to run before reaching its command timeout. Addresses #
- There is now an configuration option. When this option is , Cypress will automatically replace with a polyfill that Cypress can spy on and stub. Addresses #
- You can now pass a flag to to silence any Cypress specific output from stdout. Addresses #
Bugfixes:
- now correctly resolves when waiting for XHR requests that contain resource-like text in the XHR&#x;s query params or hash (like , ., ). #
- We fixed a regression in where errors thrown from the application under test as strings would not be correctly handled. Fixes #
- We fixed a regression in where would hang if the subject had a shadow root and was not enabled. Fixes #
- We fixed a regression in so that now properly asserts against , or element&#x;s values. Fixes #
- Cypress no longer responds with responses during a recorded when the stdout is too large. Fixes #
- We fixed an issue where Cypress could exit successfully even with failing tests when launched in global mode. Fixes #
- Assertion logs now properly display as parent commands in the Command Log regardless of what is in the hook. Fixes #
- When is enabled, querying shadow dom in certain situations will no longer cause the error during . Fixes #
- Highlighting of elements upon hover of a command in the Command Log are now visible when targeting absolute positioned elements. Fixes #
- will no longer crash when provided an empty string to the flag. Fixes #
Misc:
- There is now a loading state to indicate when tests are loading in the Command Log. Addresses #
- The type definitions for , , and have been updated to allow TypeScript types. Addresses #
- The type definitions for now correctly yield the type of the previous subject. Addresses #
- The type definitions now allow for the &#x;key&#x; keyword when chaining off &#x;any&#x; or &#x;all&#x; assertion chainers. Addresses #
Dependency Updates:
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in # and #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
Released 6/8/
Features:
Bugfixes:
- Upon domain navigation, and hooks defined in completed suites no longer erroneously rerun. Fixes #
- Errors thrown within root level hooks now correctly display in the Test Runner&#x;s Command Log. Fixes #
- We fixed a regression in where an XHR response without a body would cause Cypress to throw . Fixes #
- We fixed a regression in where using to an authenticated URL would error with Fixes #
- We now properly load code from the or when they are TypeScript files. Fixes #
- utf-8 characters now properly display within error code frames. Fixes #
- Errors thrown in a fail handler now display a stack trace and code frame pointing to the origin of the error. Fixes #
- now properly clicks on wrapped inline elements when the first child element in the parent element has no width or height. Fixes # and #
- now properly respects the option. It also better handles situations when passed a promise that never resolves. Fixes #
- When is enabled, Cypress will no longer exit with SIGABRT in certain situations. Fixes #
- We fixed a regression in where the Tests button in the Test Runner wouldn&#x;t take you back to the tests list in all browsers. Fixes #
- Using the shortcut during no longer does anything. This prevents the Test Runner from getting into a &#x;stuck&#x; state. Fixes #
Misc:
- The design of errors and some iconography displayed in the Test Runner&#x;s Command Log have been updated. Addresses #, # and #
- The commands in the Test Runner&#x;s Command Log now display in the same casing as the original command. Addresses #
- The navigation links in the Test Runner now display the correct CSS styles when focused. Addresses #
- now has TypeScript types for the option. Addresses #
- TypeScript types for options and have been updated to be more accurate. Addresses #
- TypeScript types for have been added. Addresses #
- We now display a more accurate error message when passing a browser to the flag that is not supported by Cypress. Addresses #
- We&#x;re continuing to make progress in converting our codebase from CoffeeScript to JavaScript. Addresses # in # and #
Dependency Updates:
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
Released 5/26/
Features:
- now supports an option that can be used to set the encoding of the response body, defaulting to . Addresses # and #
Bugfixes:
- We fixed a regression in where the address bar of the application under test would disappear when scrolling commands ran and the application under test would visually shift after taking screenshots. Fixes # and #
- We fixed a regression in where test runs could hang when loading spec files with source maps. Fixes #
Misc:
- We now display a more descriptive error message when the plugins file does not export a function. Addresses #
Released 5/20/
Features:
- Errors in the Test Runner now display a code frame to preview where the failure occurred with the relevant file, line number, and column number highlighted. Clicking on the file link will open the file in your preferred file opener and highlight the line and column in editors that support it. Addresses #
- Cypress now utilizes source maps to enhance the error experience. Stack traces are translated so that your source files are shown instead of the generated file that is loaded by the browser. Cypress will include an inline source map in your spec file. If you modify the preprocessor, ensure that inline source maps are enabled to get the same experience. Users of should upgrade to v or later of the package which will correctly inline source maps. Addresses #, # and #
- Cypress now enables AST-based JS/HTML rewriting when setting the configuration option to . Addresses #
- Number arguments passed to , , , , and assertions chainers are now automatically cast to strings for comparison. Addresses #
Bugfixes:
- Default TypeScript options are now set to which manicapital.com and the browser expect. This fixes a situation where setting a different module in a would cause errors to throw if you had , or keywords in your code. Fixes #, #, #, and #
- When is enabled, setting or to a relative href, or using or with a relative href will no longer navigate the AUT to the wrong URL. Fixes # and #
- When is enabled, the use of and will no longer cause the AUT to break out of the Cypress iframe. Fixes # and #
- When is enabled, calls to , , and other will no longer point to the wrong reference after being proxied through Cypress. Fixes #
- When is enabled, scripts using the attribute for sub-resource integrity (SRI) will now load after being proxied through Cypress. Fixes #
- When is enabled, the use of to set the URL will no longer navigate the AUT to the wrong URL. Fixes #
- Type definitions will no longer conflict when running Cypress in a project with Jest. Fixes #
- We increased the timeout for launching Firefox from seconds to 50 seconds. Previously, users hitting this limit would encounter a cannot open socket error; now, the error will be wrapped. Fixes #
- will now click in the correct coordinates when either x or y coordinate options are zero. Fixes #
- Cypress no longer displays when a browser can&#x;t connect. Fixes #
- You can now pass the option to to select options within a disabled . Addresses #
- We now throw an error when attempting to an within a disabled . Fixes #
- We fixed a regression in where the message output during errors were not formatted correctly. Fixes #
- Using now correctly behaves the same as Lodash&#x;s capitalize method. Fixes #
- When is enabled, clicking on a component spec now watches the correct file without assuming it is an integration file. Fixes #
- Firefox video recording no longer crashes Cypress when running very short spec files. Fixes #
- Applications containing a DOM element with an id attribute containing &#x;jquery&#x; will no longer throw an error during . Fixes #
- Long errors generated when compiling or bundling the test file are now horizontally scrollable. Fixes #
Misc:
- Cypress no longer requires write access to the root of the project, it instead will display a warning when no write access is given. Addresses #
- We increased the timeout for launching Chrome from 20 seconds to 50 seconds. Addressed in #
- We increased the timeout for macOS or Linux to exit from a command when looking for available browsers from 5 seconds to 30 seconds. Addressed in #
- We improved error handling when Cypress launches Chromium-family browsers. Addresses #
- We now export types as a partial of the full options interface. Addresses #
- We&#x;re continuing to make progress in converting our codebase from CoffeeScript to JavaScript. Addresses # in #, #, #, #, #, and #
Dependency Updates:
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in # and #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
- Upgraded from to . Addressed in #
Released 4/28/
Features:
Bugfixes:
- Custom Mocha reporters will now correctly use the version of Mocha bundled with Cypress. Fixes # and #
- We better account for word boundaries in application scripts when is . Fixes #
- Fixed an issue where iterators in TypeScript were not properly transpiled. Fixes #
Misc:
- The update window in the Test Runner now encourages yarn users to Cypress instead of to help prevent installing 2 versions of Cypress when using yarn workspaces. Addressed in #
- We&#x;re continuing to make progress in converting our codebase from CoffeeScript to JavaScript. Addresses # in # and #
Dependency Updates:
- Upgraded from to . Addressed in #
Released 4/20/
Bugfixes:
- Cypress can now launch on systems where Chromium is installed via Snapcraft. Fixes #
- We now check whether the event&#x;s target element is detached before issuing the event during . Fixes #
- We fixed a regression in where the Test Runner could send an organization ID during project setup when the default organization is preselected. Fixes #
- We fixed a regression in that caused projects to include bundled TypeScript. Fixes #
- Fixed an issue where sites that set headers would fail to load in Cypress. Fixes #
Misc:
- We fixed some extra spacing displaying below the project nav in the Test Runner. Addresses #
- The typings for run results when using the Module API now indicate they can be or . Addresses #
- We&#x;re continuing to make progress in converting our codebase from CoffeeScript to JavaScript. Addresses # in #
Released 4/13/
Features:
- TypeScript test files are now supported without using special preprocessors plugins. Addresses #
Bugfixes:
- We fixed an issue where Cypress could crash with a error when testing applications that make use of WebSockets. Fixes #
- Uncaught errors thrown from within application or test code now display their proper stack trace. Fixes #
- Assertion errors now include a stack trace that includes the calling code. Fixes #
- We now clone the object passed into Cypress commands so that they&#x;re not mutated and receive the proper . Fixes #
- We fixed an issue where invalid values could cause requests to fail with a error. Now, invalid values will be ignored. Fixes #
Misc:
- Cypress no longer hides output from , , , or commands when npm log level is or . Addresses #
- The error message is now more specific about the promise resolution value required. Addresses #
Dependency Updates:
- Upgraded from to . Addressed in #
Released 3/30/
Features:
- Errors shown in the Test Runner have a new design including an expandable stack trace, better highlighting of code elements, and &#x;Learn more&#x; links that link to relevant Cypress documentation. This is part of our larger improvements to error display with more exciting features to come. Addresses #
- When you open a Cypress project, clicking on the Settings tab and clicking into the Experiments panel will display the experimental features that are available and whether they are enabled for your project.
- Added support for setting cookie values via . Addresses #
- Added experimental support for adding values to the objects yielded from , , and . Users can enable this by setting the configuration value to . In Cypress 5, this will be the default. Addresses #
- Added support for the cookie attribute in , , and proxied HTTP requests. Addresses #
- When an assertion is retried (using ) and fails, it now shows the diff in the . Addresses #
Bugfixes:
- Fixed a regression in where cypress installation could fail if Git is not installed. Fixes #
- Fixed a regression in where certain HTTP requests could fail with or . Fixes #
- Fixed a regression in where Electron deprecation warnings were printed to stderr in open mode. Fixes #
- Cookies set with a Domain containing an unknown TLD are now sent along for all requests. For example, a cookie like will now be sent during manicapital.comt() to . Fixes #
- We fixed a situation where a cross-origin errors could incorrectly throw in Chrome. Fixes #
- Visibility checks against
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