28.02.2019
Sport Analyzer 2.1 serial key or number

Sport Analyzer 2.1 serial key or number

By  Sport Analyzer 2.1 serial key or number  0 Comments
Sport Analyzer 2.1 serial key or number

Sport Analyzer 2.1 serial key or number

Cisco Identity Services Engine Administrator Guide, Release 2.1

Manage Traditional License Files

To continue to use Cisco ISE services after the 90-day Evaluation license expires, and to support more than 100 concurrent endpoints on the network, you must obtain and register Base licenses for the number of concurrent users on your system. If you require additional functionality, you will need Plus and/or Apex licenses to enable that functionality.

Licenses are uploaded to the Primary Policy Administration Node and propagated to the other Cisco ISE nodes in the cluster. Licenses are centrally managed by the Administration node, the other nodes do not require separate licenses. If you have two Administration nodes deployed in a high-availability pair, you must ensure that each of them have the same license capabilities. Generate the license with both the UDIs of the Primary and the Secondary Policy Administration Nodes and then add the license to the Primary Policy Administration Node.

After you install the Cisco ISE software and initially configure the appliance as the PAN, you must obtain a license for Cisco ISE and then register that license. You register all licenses to the PAN via the Primary and Secondary Administration Node hardware UDI. The PAN then centrally manages all the licenses that are registered for your deployment.


Note

When a node is deregistered from the PAN, it becomes a standalone node and its license is reset to Evaluation.

This section explains how to register, re-host, renew, migrate, upgrade, and remove Traditional ISE licenses.

Cisco ISE Licensing Model

Cisco ISE licensing model allows you to purchase licenses based on your enterprise's needs. When using Traditional Licensing, you import all individual licenses and continue to manage them individually from ISE. When using Smart Licensing, you manage a centralized Cisco account, which contains all information about the different endpoint licenses you have purchased.

Valid license options include:

  • ISE Base only

  • ISE Base and Plus

  • ISE Base and Apex

  • ISE Base and Device Administration

  • ISE Base, Plus, Apex, and Device Administration

  • ISE Base, Plus, Apex and AnyConnect Apex

The number of Plus license sessions can be up to the number of Base license sessions on the deployment. The same stands for Apex license sessions. Apex and Plus licenses can be installed independently without any restriction on the number of Apex versus Plus licenses. Cisco ISE licenses are based on the number of concurrent endpoints with active network connections whereas AnyConnect Apex licenses are on a per user basis. AnyConnect Apex license count can exceed Cisco ISE Base license count.


Note

The services contained within the Plus license, most notably profiling, are frequently used across the entire deployment. When you add Plus licenses to the deployment, we recommend that the Plus license count be equal to the Base license count. However, you might have a situation where the Plus license services might not be needed across the entire deployment, which is why Cisco ISE allows the Plus license count to be less than the Base license count.

Cisco recommends installing (for Traditional Licensing), or purchasing (for Smart Licensing) Base, Plus, and Apex licenses at the same time.

  • Base licenses are required to use the services enabled by Plus and/or Apex licenses. However, you do not need a Plus license in order to have an Apex license or vice versa, since there is no overlap in their functionality.

  • When you install a Base or Mobility Upgrade license, Cisco ISE continues to use the default Evaluation license as a separate license for the remainder of its duration.

  • When you install a Mobility Upgrade license, Cisco ISE enables all Wired, Wireless, and VPN services.

  • A Base or Mobility license is required to install the Device Administration license.

  • You cannot upgrade the Evaluation license to a Plus license without first installing the Base license.

If you have not purchased a Cisco ISE VM license before, refer to the ISE Ordering Guide to choose the appropriate VM license. If you have Cisco ISE VM licenses with no associated Product Authorization Keys (PAK), contact the Cisco licensing team with the Sales Order numbers of your Cisco ISE VM purchases. Your request will be processed to provide one medium VM license key for each ISE VM purchase made.

For assistance with licensing issues of lower severity levels, open a case online through the Support Case Manager, at http://cs.co/scmswl.

For Cisco TAC assistance with critical issues, refer to the contact information provided at http://cs.co/TAC-worldwide.

ISE License Packages

Perpetual/Subscription (Terms Available)

ISE Functionality Covered

Notes

Base

Perpetual

  • Basic network access: AAA, IEEE-802.1X

  • Guest services

  • Link encryption (MACSec)

  • TrustSec

  • ISE Application Programming Interfaces

Plus

Subscription (1, 3, or 5 years)

  • Bring Your Own Device (BYOD)—when consuming either a built-in or an external certificate authority

  • MSE integration for location services

  • Profiling and Feed Services

  • Adaptive Network Control (ANC)

  • Cisco pxGrid

Does not include Base services; a Base license is required to install the Plus license.

When onboarding an endpoint with the BYOD flow, the Plus services are consumed on the active session even when related BYOD attributes are not in use.

Apex

Subscription (1, 3, or 5 years)

  • Third Party Mobile Device Management (MDM) integration

  • Posture Compliance

  • TC NAC

Does not include Base services; a Base license is required to install the Apex license.

Note 

When you use Cisco AnyConnect as unified posture agent across wired, wireless, and VPN deployments, you need Cisco AnyConnect Apex user licenses in addition to Cisco ISE Apex licenses.

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, Sport Analyzer 2.1 serial key or number

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Sport Analyzer 2.1 serial key or number

Advanced Link Analyzer User Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.1

Advanced Link Analyzer is a high-speed transceiver link simulation. When you design high-speed, multi-gigabit transceiver links, you must ensure the end-to-end performance from transmitter (TX) to receiver (RX) and all interconnects in between.

Advanced Link Analyzer's graphical user interface (GUI) and link simulator allow you to quickly and easily set up and evaluate high-speed link performance early in your design cycle. Advanced Link Analyzer also helps you identify possible issues in board level design. With Advanced Link Analyzer, you can quickly estimate optimal link equalization and other electrical parameter settings for transmitter and receiver. You can also use Advanced Link Analyzer to predict link performance such as jitter and noise at a small probability level.

Advanced Link Analyzer has the following minimum system requirements:

  • Microsoft Windows 7, Windows 8, Windows 10, Windows Server 2008, Windows Server 2012, and Windows Server 2016
  • 4 GB RAM
  • 8 GB storage space
  • Microsoft .NET Framework 4.8

Advanced Link Analyzer requires an Intel® Quartus® Prime software pro/standard license to perform simulations, design channels, and view channel characteristics. Contact My Intel® support if you have questions regarding accessing the Intel® Quartus® Prime software pro/standard license.

Note:Advanced Link Analyzer (was called JNEye) 15.0 and older versions require a Quartus II subscription license to perform simulations, design channels, and view channel characteristics.

To install Advanced Link Analyzer, perform the following steps:

  1. Acquire the current version of the Advanced Link Analyzer Installation Package from the Intel Download Center.
    1. Go to the IntelDownload Center.
    2. Click Select by Software.
    3. Select Select Software Products > Intel®Advanced Link Analyzer.
    4. Select Select Version or Product > <current version>.
    5. Click Download. This leads to the Advanced Link Analyzer download page where you choose the version (Pro or Standard) to download.
  2. Execute the installation file to install Advanced Link Analyzer.
  3. Execute Advanced Link Analyzer.exe to start Advanced Link Analyzer. Advanced Link Analyzer comes with both 32-bit and 64-bit executables. 32-bit Advanced Link Analyzer is located in <Advanced Link Analyzer Installation Directory>\bin and 64-bit Advanced Link Analyzer is in <Advanced Link Analyzer Installation Directory>\bin64. For example, the most common installation folder for 64-bit is C:\intelFPGA_pro_ala\<current version>\adv_link_analyzer\bin64.
  4. Starting with the 19.3 version, the Advanced Link Analyzer installation directory is write-protected so that no data or files can be created or modified in it.

Due to the write protection, some legacy Intel® IBIS-AMI models, for example, Intel® Stratix® 10 L-tile and H-tile receiver models, can cause issues during simulations. This does not happen universally, and the issues depend on your computer’s security and access control settings. As a work around, you can do one of the following:

  • Get administration write access to your account or computer. You may need to contact your IT support for this option.
  • Copy your Advanced Link Analyzer installation to somewhere outside the original installation folder. For example, you can copy your installation from to , and then change the new folder’s (include folder, sub-folders, and files) attributes so that it is not read-only. Launch Advanced Link Analyzer from this new location.

Intel recommends that you install and run Advanced Link Analyzer in local storage space. Because Advanced Link Analyzer can create temporary working files in storage space, simulation speed can be impacted if the installation or temporary files are located in a network drive or remote storage space. If you need to use remote storage space, Advanced Link Analyzer provides an option to specify the simulation working directory. You can configure your local storage space as the simulation working directory to improve simulation speed. See System Options for details.

Advanced Link Analyzer requires an Intel® Quartus® Prime software license to perform simulations, design channels, and view channel characteristics. Contact My Intel support if you have questions regarding accessing the Intel® Quartus® Prime software pro/standard license.

Note:Advanced Link Analyzer (was called JNEye) 15.0 and older versions require a Quartus II subscription license to perform simulations, design channels, and view channel characteristics.

Advanced Link Analyzer automatically checks the license server specified in the system environment variable for the required license. The license checking configuration can be configured by editing the following entries in the configuration file JNEye_Config.dat:

  • %% LM_License_File_Name—License file name. If a license file is specified, Advanced Link Analyzer validates the license in this file. If the license is not valid, the license server (specified in ) is used. The default value is .
  • %% LM_License_Feature_Name—The feature or type of license to be checked out for Advanced Link Analyzer use. The default value is quartus.

The JNEye_Config.dat file is located in Advanced Link Analyzer's C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\ <current version> folders.

When you execute Advanced Link Analyzer for the first time, Advanced Link Analyzer may ask permission to create an Advanced Link Analyzer working directory at C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<current version>\GUI_Work.

Click Yes to use the default location. To use a different working directory:
  1. Exit Advanced Link Analyzer.
  2. Create an environment variable , and specify the full path name of desired work directory location.
  3. Start Advanced Link Analyzer. Advanced Link Analyzer asks you to create a work directory in the specified location.
  4. Click Yes to complete.

If you have problems running Advanced Link Analyzer after installing the program, follow these instructions:

  • Verify that Microsoft Visual C++ 2017 library is installed on your system. If you execute Advanced Link Analyzer in a system that does not have the Microsoft Visual C++ 2017 library, you get an error message.
    • If you do not have the Visual C++ 2017 library installed, download it from the Microsoft web site, and install it.
      Note: For 64-bit Windows operating systems, the 32-bit version of the Visual C++ 2017 library is required for running the 32-bit version of the Advanced Link Analyzer.
  • Verify that the Microsoft .NET Framework 4.8 is installed on your system. If you execute Advanced Link Analyzer in a system that does not have Microsoft .NET Framework 4.8, you get an error message.
    • You may have to install Windows Imaging Component (WIC) before installing .NET Framework 4.8. You can download WIC from the Microsoft web site.
    • Download .NET Framework 4.8 from the Microsoft web site, and install it.

Advanced Link Analyzer comes with the following executable files:

  • adv_link_analyzer.exe—Advanced Link Analyzer’s main user interface
  • adv_link_analyzer_sim_eng.exe—Advanced Link Analyzer simulation engine
  • adv_link_analyzer_sim_eng_console.exe—Advanced Link Analyzer simulation engine (console version)
  • adv_link_analyzer_data_viewer.exe—The Advanced Link Analyzer Data Viewer displays simulation results
  • adv_link_analyzer_channel_viewer.exe—The Advanced Link Analyzer Channel Viewer displays channel characteristics
  • adv_link_analyzer_batch_sim.exe—The Advanced Link Analyzer Batch Simulation Controller runs simulations in batch mode
  • adv_link_analyzer_channel_designer.exe—Advanced Link Analyzer’s channel designer that generate S-parameter channel models for link simulations

Advanced Link Analyzer uses the following file extensions:

  • .jne—Advanced Link Analyzer simulation configuration
  • .jneschm—Advanced Link Analyzer simulation schematic configuration
  • .jnetxdata, .jnerxdata, .jnedevdata, .jneledata, and others—Advanced Link Analyzer internal data

There are two ways to share an Advanced Link Analyzer project:

  • Project Archiver/Project Unarchiver method: Project Archiver and Project Unarchiver are GUI-based functions that collect and package channel model files, device model files (if applicable), and link settings in a single data file for sharing. See Archiving and Unarchiving Projects for details.
  • Manual method: Both .jne and .jneschm files are needed for other users to reload the link configuration in their Advanced Link Analyzer session. Make sure all other associated files, such as channel model files and device model files, are available or included so that simulations can run correctly.

Advanced Link Analyzer provides limited backward compatibility with link configuration files saved in previous versions.

  1. Click the Advanced Link Analyzer logo located in the upper left of the main GUI to open the license/version window.
  2. Click the User Guide button in version/license window.
Double-click the adv_link_analyzer.exe icon to launch Advanced Link Analyzer.
Figure 1. Advanced Link Analyzer Control Module

The Link Designer module allows you to construct communication links.

Figure 2. Advanced Link Analyzer Link Designer Module

Transmitter (TX) Component

Channel/Link Component

Receiver (RX) Component

Intel® Agilex™

  • Intel® Agilex™ E-tile (wrapper support)
  • Intel® Agilex™ P-tile (wrapper support)

Stratix®

  • Stratix® V GX
  • Stratix® V GT
  • Intel® Stratix® 10 L-tile
  • Intel® Stratix® 10 H-tile
  • Intel® Stratix® 10 E-tile (wrapper support)
  • Intel® Stratix® 10 P-tile (wrapper support)

Arria®

  • Arria® V GZ
  • Intel® Arria® 10 GX/SX
  • Intel® Arria® 10 GT

Generic

  • Custom
  • PCI Express* 8 GT
  • PCI Express* 16 GT

IBIS-AMI

Channel

  • Transmission
  • Connector
  • Package

Crosstalk

  • Far-end Crosstalk
  • Near-end Crosstalk
  • Far-end Crosstalk w/ Aggressor
  • Near-end Crosstalk w/ Aggressor
  • Aggressor Transmission w/ Aggressor

Channel Designer

  • Stripline
  • Microstrip
  • Coax RLGC
  • Ideal Transmission Line
  • PCB Via
  • Coupled Stripline
  • Coupled Microstrip
  • Channel Designer Module
  • PCB Stackup

Basic Component

  • AC Coupling Capacitor
  • Shunt Capacitor
  • Series Inductor
Link Component
  • Repeater/Retimer TX
  • Repeater/Retimer RX
  • Noise Source w/ Channel

Intel® Agilex™

  • Intel® Agilex™ E-tile (wrapper support)
  • Intel® Agilex™ P-tile (wrapper support)

Stratix®

  • Stratix® V GX
  • Stratix® V GT
  • Intel® Stratix® 10 L-tile (wrapper support)
  • Intel® Stratix® 10 H-tile (wrapper support)
  • Intel® Stratix® 10 E-tile (wrapper support)
  • Intel® Stratix® 10 P-tile (wrapper support)

Arria®

  • Arria® V GZ
  • Intel® Arria® 10 GX/SX
  • Intel® Arria® 10 GT

Generic

  • Custom
  • PCI Express* 8GT
  • PCI Express* 16 GT

IBIS-AMI

Advanced Link Analyzer supports the following simulations:

  • Intel TX to Intel RX
  • Intel TX to non-Intel RX
  • Non-Intel TX to Intel RX
Note:
  • Non-Intel to non-Intel link simulations are not supported.
  • For Intel® devices that are not listed in Table 1, contact My Intel® support, and acquire the IBIS-AMI models.
  • Devices supported with wrapper technology can be added, removed or updated to Advanced Link Analyzer after the tool is installed. Please refer to IBIS-AMI Wrapper for further details.

A link consists of a transmitter, a receiver, and one or more channel/link components. Select the transmitter, receiver, and channel/link components from the menus at the top of the Link Designer workspace.

After the link components are placed into the workspace, click Connect to connect the components. In connect mode, one or two connectors are shown on each component. Connect the link components by dragging the line from one connector to another. Two types of connections are provided in Link Designer: Right Angled Line and Straight Line. Right Angled Line is the default connection method. Test points can be manually placed into the link by clicking Test Point and connecting to the desired location in the link.

The following rules of link construction apply to the Link Designer module:

  • A transmitter can only have one output port or connector
  • A receiver can only have one input port or connector
  • A channel/link component has one input and one output port
  • A test point can only be connected to an input port
  • A connection between two components can be established from an output port to an input port
  • A transmitter cannot be connected directly to a receiver

A link establishment checking algorithm runs constantly in the background, checking whether a link is established for simulations. When a link is established between a transmitter and receiver, the link lines become bold and color-coded. Bold black lines indicate signal paths, green lines indicate crosstalk signal paths, and purple lines point to test point port locations. The following figure shows an example link topology. A table of link components is displayed in the Channel tab for reference.

Figure 3. Advanced Link Analyzer Link Designer with Channel Table

When a channel component (for example, a transmission line, connector, far-end crosstalk (FEXT), near-end crosstalk (NEXT), package, AC coupling capacitor, or shunt capacitor) is chosen, the Channel Wizard helps you verify or set the channel configuration.

Figure 4. Advanced Link Analyzer Channel Wizard

The Channel Wizard displays the channel characteristics and allows you to verify the correctness of the channel component, such as a component represented by an S-parameter. The Channel Wizard allows you to select the following components:

  • channel type
  • port configuration
  • signal lanes (for multiple-lane S-parameters with eight and more ports)
  • crosstalk aggressor location (for multiple-lane S-parameters)
  • aggressor
  • series inductance value (in nH)
  • AC coupling capacitor value (in nF)
  • shunt capacitance value (in pF)

The Channel Wizard checks the integrity of the channel component in terms of passivity and causality characteristics. When the Channel Wizard detects passivity and causality violations, it displays messages about the severity of the violations in the text box on the left of the OK button. The levels of channel integrity violation are listed in the following tables. Advanced Link Analyzer provides the option to enforce or improve causality of the selected channel during a simulation when Enforce Causality is turned on.

Note: Channel integrity checking can be disabled or bypassed by setting Channel Integrity Check in the System Options window. We have found that Advanced Link Analyzer's Channel Integrity Checking algorithm is compatible and reliable for majority of channels. However, we also saw some exceptions, such as a S-parameter with an extensive amount of measurement noise across frequencies, that can lead to computation convergence issues. If this is the case, please disable Channel Integrity Checking.
Passivity Violation Check ResultsImpact on Link Simulation Accuracy Recommendations
No Passivity ViolationNo impactNo action needed
Slight Passivity ViolationThere may not be a noticeable effect in the simulation result.The channel model can be further improved but the improvement in terms of simulation results accuracy can be small.
Minor Passivity ViolationThere may be a noticeable effect in the simulation result.The channel model can be further improved. Simulation result accuracy can be reduced.
Passivity ViolationSimulation result impactThe channel model needs to be regenerated (by design tools) or re-taken (by instruments). The confidence of simulation results using this channel model is low.
Causality Violation Check ResultsImpact on Link Simulation AccuracyRecommendations
Channel is causalNo impactNo action needed
Slight non-causalThere may not be a noticeable effect in the simulation resultThe channel model can be further improved but the improvement in terms of simulation results accuracy can be small.
Somewhat non-causalThere may be a noticeable effect in the simulation resultThe channel model can be further improved. Simulation result accuracy can be reduced.
Non-causalSimulation result impactThe channel model needs to be regenerated (by design tools) or re-taken (by instruments). The confidence of simulation results using this channel model is low.
To select another S-parameter within the Channel Wizard, click Change Channel.
Note:Intel recommends that you replace or change a channel with one of the same channel type. Link Designer allows channel changing with different channel types, but you might see inconsistent channel icons in the design workspace.

An existing channel can be changed by adding a new channel component or by modifying an existing channel component. Right-click in the Link designer module and select Properties.

When using the package channel component, follow these guidelines:

  • Package models should be placed next to the devices.
  • Each device can have only one package model. Therefore, the external package model can only be used when the device’s package type is “Custom”.
  • The package model type is used by the simulation engine to identify the boundary of the devices and generate a waveform for observation and analysis.
  • The package model is treated the same way as the “Transmission” channel type. Therefore, use the “Transmission” channel type even if the model represents a physical package (in your system) but it is not a package of the TX and RX.

The Link and Simulation Setting tab sets the global link parameters and simulation configurations.

Figure 5. Link and Simulation Setting Tab

The Link and Simulation Setting dialog box contains the following fields.

Data Rate

Link data rate is specified in Gbps.

Simulation Length

Simulation length is specified in the number of bits running at the specified data rate. Simulation length should be at least 4096 bits. Intel recommends that the length is a power-of-2 factor for the best computation efficiency. The simulation length does not apply in Statistical mode.

Note: Simulation length is adjusted automatically to the closest power-of-2 factor.

Target BER

Target bit error rate (BER) is used to calculate the jitter and noise at low BER conditions. If the simulation length is greater than the inverse of the target BER, the link performance is directly assessed and calculated. If the simulation length is shorter than the inverse of the specified target BER, Advanced Link Analyzer uses specific methodology and algorithms to calculate the link performance. The methodology of jitter and noise at low BER can be found in HST Jitter and BER Estimator Tool User Guide for Stratix® IV GT and GX Devices.

Test Pattern

Allows you to specify the test pattern used in the simulation. The following test patterns are available:

  • PRBS-7, PRBS-9, PRBS-11, PRBS-15, PRBS-23, PRBS-31, and QPRBS13-CEI
    • The PRBS test patterns are generated using Advanced Link Analyzer’s built-in pattern generator.
    • If the whole PRBS pattern is shorter than the simulation length, the PRBS pattern is inverted and repeated. The inversion is applied to achieve DC balance of the generated PRBS test pattern.
    • If the PRBS patterns are longer than the simulation length, a partial test pattern of the PRBS pattern is used. The default initial condition of PRBS test pattern generation is with logic 1s in all shift registers for the valid PRBS patterns.
    • The most commonly used PRBS test patterns are listed in the Test Pattern menu. Other PRBS test pattern can be selected or configured in the Pattern Designer.

  • Pattern Designer—Allows you to specify your own custom test patterns. The following figure shows the Pattern Designer user interface.

    Figure 6. Advanced Link Analyzer Pattern Designer

    The Pattern Designer includes the following test pattern generation methods:

    • PRBS—Provides an extensive list of common PRBS test patterns. You can also specify custom PRBS polynomials and seeds. The internal linear feedback shift register (LFSR) engine uses the information to generate the desired test pattern. Other options include selecting how the test pattern is repeated or extracted when the simulation length is longer or shorter than the generated test patterns. There are two options for selecting the partial test patterns:
      • Use First Part of Generated PRBS Sequence
      • Include Longest Run-Length Bit Sequence—The longest run-length test pattern is located at the ending portion of the test bit sequence.
    • Consecutive Bit Patterns—Defines the test patterns with repeating patterns.
    • Clock—Generates a clock-like pattern.
    • All 1's—Generates an all-ones test pattern that usually feeds into a coder or scrambler.
    • All 0's—Generates an all-zeros test pattern that usually feeds into a coder or scrambler.
    • Encoder and Scrambler—Advanced Link Analyzer supports the following encoders and scramblers: 8B/10B, 64B/66B, 64B/67B, and 128B/130B.
  • Custom—Click the open-file dialog button to select a custom test pattern file.
    Figure 7. Custom Test Pattern File Browser Button

    The custom pattern files are in the following formats:

    • Hexadecimal—Hexadecimal strings start with 0x. For example, a PRBS-7 test pattern can be specified by 0x8cd501fbe7ae1ba62b05e3b64a4272d0. The custom file name must have a .hex extension.
    • Binary—Binary strings have a format such as "001000111…". Blank characters and new lines/returns are allowed in the input binary string file. The custom file name must have a .bin extension.
    Note: The custom test pattern has a maximum text length of 262,142 characters (about 1M bits with a hexadecimal text format or about 246K bits with a binary text format). Intel recommends that the test pattern string (hexadecimal or binary) is specified in a single row without spaces, especially for long custom test patterns. If a custom test pattern is input with multiple lines of text, the line returns or end-of-line control characters on each line of text are counted as an item or entry by the text parser.

Modulation Scheme

Advanced Link Analyzer support NRZ and PAM4 modulation schemes. Choose PAM4 only when the device supports it.

Forward Error Correction (FEC)

FEC is a coding scheme that encodes the data pattern with additional code words that can help the receiver to recover bit errors. Intel® Arria® 10 and Intel® Stratix® 10 devices support FEC schemes. In Advanced Link Analyzer, the FireCode, Reed-Solomon RS (528, 514), and RS (544, 514) FEC models are supported. When FEC is enabled, Advanced Link Analyzer produces additional FEC related results. The default FEC setting is Off.

Reference Clock

You can specify the reference clock that feeds into the transmitter. The supported clock frequencies are shown in MHz. By default, the reference clock is assumed to be ideal without any noise or jitter. You can configure and specify the reference clock characteristics by clicking Reference Clock Option.

Note: If the reference clock is ideal (default setting), the reference clock frequency does not affect the simulation result.

The reference clock can be fed to a transmitter with or without enabling a phase-locked loop (PLL) module. When the transmitter PLL is disabled or not present, the reference clock noise and jitter directly affect the serial output signal.

With integer PLLs, Advanced Link Analyzer supports an integer divider ratio between the data rate and the reference clock frequency. If the ratio is not an integer, the reference clock frequency is rounded to the closest integer-divided-ratio frequency. The actual reference clock frequency used in the simulation is displayed in the message box next to the pull-down menu. With fractional-N PLLs, fractional divider ratios are allowed.

In the simulation with specific transmitter devices, such as Intel® Arria® 10 GX/SX/GT, Stratix® V GT, Stratix® V GX, and Arria® V GZ devices, the supported data rate to reference clock divider ratios are limited. If a specific combination of data rate, PLL divider ratio, and reference clock frequency cannot be found, the reference clock used in the simulation can be further adjusted.

The reference clock frequencies listed are commonly used in most serial link protocols. If you cannot find the exact reference clock frequency from the list, you can add your reference clock frequency with the following procedure:

  1. Close Advanced Link Analyzer.
  2. Navigate to the Advanced Link Analyzer installation directory. Typically, Advanced Link Analyzer is installed in C:\intelFPGApro\<version number>\adv_link_analyzer\.
  3. Under the Database folder, find RefCLK_List.jnetxdata.
  4. Copy RefCLK_List.jnetxdata to your local directory (typically at C:\Users\<Your User or Account Name>\AdvancedLinkAnalyzer\<current version>\Database\.
  5. Edit the file by adding your desired reference clock frequencies.
  6. Save the change and exit the editor.
  7. Restart Advanced Link Analyzer.

Reference Clock Option

The reference clock option user interface allows you to configure the characteristics of the reference clock used in the simulation. The reference clock can be specified with the following methods:

  • Ideal Reference Clock—With this setting, the reference clock is ideal without any noise or jitter.
    Figure 8. Ideal Reference Clock Setting
  • Option 1: Reference Clock Jitter
    Figure 9. Reference Clock Option 1: Reference Clock Jitter

Option 1 configures the reference clock with the following options:

  • Random Jitter— Specify the frequency range (in ps).
    Note:Intel recommends that the maximum frequency range (fMAX) of the phase noise be set to the reference clock frequency. If the fMAX is less than the reference clock frequency, Advanced Link Analyzer uses linear extrapolation to calculate the phase noise at fMAX, which can lead to inaccurate results.
  • Periodic Jitter Type—Specify the shape profile, frequency (in Hz), and amplitude (in ps). The shape profile can be:
    • Triangle
    • Hershey with programmable Hershey shape parameter
    • Sharkfin with programmable Sharkfin shape parameter
    • Sinusoidal
  • Spurs—Specify clock spectrum spurs with individual frequency (in Hz) and amplitude (in dBc). For example, if the reference clock has three spurs: –110 dBc at 100 kHz, –90 dBc at 1 MHz, and –80 dBc at 10 MHz, you can input the following text into the Spurs text box: 100e3 -1101e6 -9010e6 -80
  • Spur Phase Offset

    Use the Spur Phase Offset pull-down menu to configure the initial phase of spur noises. The options are:

    • Auto—Advanced Link Analyzer automatically selects the default initial spur noise phase. The default initial spur phase is 0 rad.
    • Random—Advanced Link Analyzer randomly sets the initial spur noise phases.
    • Zero—Advanced Link Analyzer sets the initial spur noise phase to 0 rad.
    • Specified—You can manually specify the initial spur phase individually by adding the phase value after the amplitude value. The following example shows the initial spur noise phases are 1.0, 2.0, and 3.0 rad. 100e3 -110 1.01e6 -90 2.010e6 -80 3.0
  • Option 2: Phase Noise
    Figure 10. Reference Clock Option 2: Phase Noise

Option 2 configures the reference clock with the following options:

  • Phase Noise—Specify reference clock jitter using a phase noise profile. Reference clock phase noise is specified with the noise power spectrum described with frequency and amplitude. The above figure demonstrates a phase noise profile with a measured reference clock phase noise data set.
    Note:Intel recommends that the maximum frequency range (fMAX) of the phase noise be set to the reference clock frequency. If the fMAX is less than the reference clock frequency, Advanced Link Analyzer uses linear extrapolation to calculate the phase noise at fMAX, which can lead to inaccurate results.
  • Spurs—Specify clock spectrum spurs with individual frequency (in Hz) and amplitude (in dBc). For example, if the reference clock has three spurs: –80 dBc at 100 kHz, –90 dBc at 1 MHz, and –96 dBc at 10 MHz, you can input the following text into the text box: 100e3 -801e6 -9010e6 -96
  • Spur Phase Offset—Same as in Option 1 Reference Clock Jitter.
  • Periodic Jitter Type—Same as in Option 1 Reference Clock Jitter.
  • Plot / Update Plot—You can plot the input phase noise and spurs in the plotting area and confirm the reference clock characteristics.

Link Optimization Method

Advanced Link Analyzer can find optimal transmitter and receiver equalization settings with a user-specified link configuration.

Note: The TX/RX joint link optimization function is supported for all of Advanced Link Analyzer's native Intel device models: Stratix® V GX/GT, Arria® V GZ, Intel® Arria® 10 GX/SX/GT, and Custom transmitter/receiver. Link optimization support for IBIS-AMI models is limited.

Transmitter Mode

Receiver Mode

Notes

Manual

Manual

Both TX and RX equalizations are manually set.

Auto /

Auto with Manual Starting Point

Manual

Advanced Link Analyzer finds optimal TX equalization setting. RX EQ setting is manually set.

Manual

Auto

TX EQ is manually set. Advanced Link Analyzer finds optimal RX EQ setting.

Auto /

Auto with Manual Starting Point

Auto

Advanced Link Analyzer finds both TX and RX EQ settings.

Advanced Link Analyzer has four link optimization methods for finding the optimal link setting, such as a transmitter pre-emphasis and receiver CTLE and DFE with a given link configuration.

  • FIR=>CTLE=>DFE— (default) Optimizes the link performance by finding the optimal transmitter setting, receiver equalization setting, or both. This method prioritizes the transmitter equalization, such as pre-emphasis, de-emphasis, or FIR-based, over receiver equalization schemes. However, the optimization algorithm is also capable of detecting and utilizing optimal receiver equalization. In practice, this usually implies that most of the "heavy-lifting" in channel compensation is performed by the transmitter equalization.
  • FIR=>CTLE+DFE—Extends the FIR=>CTLE=>DFE method by enabling RX DFE (Decision Feedback Equalizer) when RX optimization is performed. This method exploits DFE capabilities by possibly reducing the channel compensation from CTLE (depending on the channel characteristics).
  • CTLE=>FIR=>DFE
Источник: [https://torrent-igruha.org/3551-portal.html]
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