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In computing, serial presence detect (SPD) is a standardized way to automatically access information about a memory module. Earlier pin SIMMs included five pins that provided five bits of parallel presence detect (PPD) data, but the pin DIMM standard changed to a serial presence detect to encode much more information.^[1]

When an ordinary modern computer is turned on, it starts by doing a power-on self-test (POST). Since about the mids, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what memory timings to use to access the memory.

Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose settings, selectively modify memory timings, or possibly to completely over-ride the SPD data (see overclocking).

Stored information[edit]

For a memory module to support SPD, the JEDEC standards require that certain parameters be in the lower bytes of an EEPROM located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. Devices utilizing the memory automatically determine key parameters of the module by reading this information. For example, the SPD data on an SDRAM module might provide information about the CAS latency so the system can set this correctly without user intervention.

The SPD EEPROM is accessed using SMBus, a variant of the I²C protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.

SPD EEPROMs also respond to I²C addresses 0x30–0x37 if they have not been write protected, and an extension (TSE series) uses addresses 0x18–0x1F to access an optional on-chip temperature sensor. All those values are seven-bit I²C addresses formed by a Device Type Identifier Code prefix (DTIC) with SA to read () from slot 3, one uses . With a final R/W bit it forms the 8-bit Device Select Code.^[2] Note that the semantics of slot-id is different for write-protection operations: for them they can be not passed by the SA pins at all.^[3]

Before SPD, memory chips were spotted with parallel presence detect (PPD). PPD used a separate pin for each bit of information, which meant that only the speed and density of the memory module could be stored because of the limited space for pins.

SDR SDRAM[edit]

Memory device on an SDRAM module, containing SPD data (red circled)

The first SPD specification was issued by JEDEC and tightened up by Intel as part of its PC memory specification.^[4] Most values specified are in binary-coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and A most significant nibble of 0 is reserved to represent "undefined".

The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.

DDR SDRAM[edit]

The DDR DIMM SPD format is an extension of the SDR SDRAM format. Mostly, parameter ranges are rescaled to accommodate higher speeds.

DDR2 SDRAM[edit]

The DDR2 SPD standard makes a number of changes, but is roughly similar to the above. One notable deletion is the confusing and little-used support for DIMMs with two ranks of different sizes.

For cycle time fields (bytes 9, 23, 25 and 49), which are encoded in BCD, some additional encodings are defined for the tenths digit to represent some common timings exactly:

DDR3 SDRAM[edit]

The DDR3 SDRAM standard significantly overhauls and simplifies the SPD contents layout. Instead of a number of BCD-encoded nanosecond fields, some "timebase" units are specified to high precision, and various timing parameters are encoded as multiples of that base unit.^[8] Further, the practice of specifying different time values depending on the CAS latency has been dropped; now there are just a single set of timing parameters.

Revision lets some parameters be expressed as a "medium time base" value plus a (signed, − +) "fine time base" correction. Generally, the medium time base is 1/8 ns ( ps), and the fine time base is 1, or 5 ps. For compatibility with earlier versions that lack the correction, the medium time base number is usually rounded up and the correction is negative. Values that work this way are:

The memory capacity of a module can be computed from bytes 4, 7 and 8. The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank. That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).

DDR4 SDRAM[edit]

The DDR4 SDRAM "Annex L" standard for SPD changes the EEPROM module used. Instead of the old AT24Ccompatible byte EEPROMs, JEDEC now defines a new nonstandard EE type with two pages at the SMBus level each with bytes. The new memory still uses the old 0xx57 addresses, but two additional address at 0x36 (SPA0) and 0x37 (SPA1) are now used to receive commands to select the currently-active page for the bus, a form of bank switching.^[11] Internally each logical page is further divided into two physical blocks of bytes each, totaling four blocks and bytes.^[12] Other semantics for "special" address ranges remain the same, although write protection is now addressed by blocks and a high voltage at SA0 is now required to change its status.^[13]

Annex L defines a few different layouts that can be plugged into a byte (of which a maximum of bytes are defined) template, depending on the type of the memory module. The bit definitions are similar to DDR3.^[12]

Extensions[edit]

The JEDEC standard only specifies some of the SPD bytes. The truly critical data fits into the first 64 bytes,^{[6][7][15][16][17]} while some of the remainder is earmarked for manufacturer identification. However, a byte EEPROM is generally provided. A number of uses have been made of the remaining space.

Enhanced Performance Profiles (EPP)[edit]

Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed.

Enhanced Performance Profiles is an extension of SPD, developed by Nvidia and Corsair, which includes additional information for higher-performance operation of DDR2 SDRAM, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes , which are unused by standard DDR2 SPD.^[18]

The parameters are particularly designed to fit the memory controller on the nForce 5, nForce 6 and nForce 7 chipsets. Nvidia encourages support for EPP in the BIOS for its high-end motherboard chipsets. This is intended to provide "one-click overclocking" to get better performance with minimal effort.

Nvidia's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory".^[19] The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video. One can use EPP/SLI memory with a single video card (even a non-Nvidia card), and one can run a multi-card SLI video setup without EPP/SLI memory.

An extended version, EPP , supports DDR3 memory as well.^[20]

Extreme Memory Profile (XMP)[edit]

A similar, Intel-developed JEDEC SPD extension was developed for DDR3 SDRAM DIMMs, later used in DDR4 also. XMP uses bytes –, which are unallocated by JEDEC, to encode higher-performance memory timings.^[21]

Later, AMD developed AMP, an equivalent technology to XMP, for use in its "Radeon Memory" line of memory modules optimized for use in AMD platforms.^[22][23] Furthermore, motherboard developers implemented their own technologies to allow their AMD-based motherboards to read XMP profiles: MSI offers A-XMP,^[24] ASUS has DOCP (Dynamic Over Clock Profiles), and Gigabyte has EOCP (Extended Over Clock Profiles).^[25]

The header contains the following data. Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns). Many other later timing values are expressed as an integer number of MTB units.

Also included in the header is the number of DIMMs per memory channel that the profile is designed to support; including more DIMMs may not work well.

All data above are for DDR3 (XMP ); DDR4 specs are not yet available.

Vendor-specific memory[edit]

A common misuse is to write information to certain memory regions to bind vendor-specific memory modules to a specific system. Fujitsu Technology Solutions is known to do this. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot).

This is the output of a &#;MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" string. The system BIOS rejects memory modules that don't have this information starting at offset h.

Some Packard Bell AMD laptops also use this method, in this case the symptoms can vary but it can lead to a flashing cursor rather than a beep pattern. Incidentally this can also be a symptom of BIOS corruption as well.^[27] Though upgrading a 2GB to a 4GB can also lead to issues.

Reading and writing SPD information[edit]

Memory module manufacturers write the SPD information to the EEPROM on the module. Motherboard BIOSes read the SPD information to configure the memory controller. There exist several programs that are able to read and modify SPD information on most, but not all motherboard chipsets.

• dmidecode program that can decode information about memory (and other things) and runs on Linux, FreeBSD, NetBSD, OpenBSD, BeOS, Cygwin and Solaris. dmidecode does not access SPD information directly; it reports the BIOS data about the memory.^[28] This information may be limited or incorrect.
• On Linux systems, the user space program decode-dimms provided with i2c-tools decodes and prints information on any memory with SPD information in the computer.^[29] It requires SMBus controller support in the kernel, the EEPROM kernel driver, and also that the SPD EEPROMs are connected to the SMBus. On older Linux distributions, manicapital.com was available as part of lm_sensors.
• OpenBSD has included a driver (spdmem(4)) since version to provide information about memory modules. The driver was ported from NetBSD, where it is available since release
• Coreboot reads and uses SPD information to initialize all memory controllers in a computer with timing, size and other properties.
• Windows systems use programs like HWiNFO32,^[30]CPU-Z and Speccy, which can read and display DRAM module information from SPD.

Chipset-independent reading and writing of SPD information is done by accessing the memory's EEPROM directly with eeprom programmer hardware and software.

A not so common use for old laptops is as generic SMBus readers, as the internal EEPROM on the module can be disabled once the BIOS has read it so the bus is essentially available for use. The method used is to pull low the A0,A1 lines so the internal memory shuts down, allowing the external device to access the SMBus. Once this is done, a custom Linux build or DOS application can then access the external device. A common use is recovering data from LCD panel memory chips to retrofit a generic panel into a proprietary laptop. On some chips it is also a good idea to separate write protect lines so that the onboard chips do not get wiped during reprogramming. A related technique is rewriting the chip on webcams often included with many laptops as the bus speed is substantially higher and can even be modified so that 25x compatible chips can be read back for later cloning of the uEFI in the event of a chip failure.

This unfortunately only works on DDR3 and below, as DDR4 uses different security and can usually only be read. Its possible to use a tool like SPDTool or similar and replace the chip with one that has its WP line free so it can be altered in situ. On some chipsets the message "Incompatible SMBus driver?" may be seen so read is also prevented.

On older equipment[edit]

Some older equipment require the use of SIMMs with parallel presence detect (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding, IBM computers and Hewlett-PackardLaserJet and other printers in particular.

See also[edit]

References[edit]